linear feedback shift register
Core function: SIM::lfsr.generate()
More...
linear feedback shift register
Core function: SIM::lfsr.generate()
itpp::LFSR derived class with clocked interface
- Note
- itpp::LFSR is in the Fibonacci form
Example: 1+X3+X4 for PRBS sequence = 2^4-1
set_prbs(4) -> set_poly with a bpoly=bvec("1 0 0 1 1");
1 + X3+X4
0 1 2 3 4
[1 0 0 1 1]
By definition there is no X^0 cell - first cell - state[0] is represented by X^1.
Threfore for LFSR of lenght N, state is bvec with lenght of (N-1)
The implementation is like J.83B standard p.9 -> PRBS randomizer
For one active tick ce[i] a single symbol represented as bvec with symbol_size = W bits is created:
y[i,:] = [x0(W-1), x0(W-2),...,x0(1), x0(0)] (default: reversed = true - x0(0) is oldest bit as for a generation time)
where each x0 bit is calculated as:
{ bin x0 = state[0:N-1] * bpoly[1:N]; state.shift_right(x0); return x0; }
Output y for ce[M] ticks is bmat with a size y = bmat[M,W]
-
rev_flag controls if output is reversed, default value of rev_flag is TRUE
-
when output is revesed symbols s[k+1] = [b[n+5],b[n+4],b[n+3]], s[k] = [b[n+2],b[n+1],b[n]]
can be easily be used in BERT synchronization [s[k+1]|s[k]], because time scale is continous
| bmat SIM::lfsr::generate |
( |
const bvec & |
ce | ) |
|
for active clock ticks [ce] generate one symbol (W bits) in output bmat y
- Parameters
-
| ce | - [bvec] - clock enable vector - sizeof(ce)=N |
- Returns
- y - [bmat] - output symbols matrix - sizeof(y)=[N,W]
| bvec SIM::lfsr::get_output |
( |
void |
| ) |
|
get initial/idle output vector
- Returns
- - [bvec] y0 ,sizeof(y0)=W
| bvec SIM::lfsr::get_poly |
( |
void |
| ) |
|
get connection poly
- Returns
- - [bvec] y0 = yout
| bvec SIM::lfsr::get_reset_state |
( |
| ) |
|
get reset state binary vector
- Returns
- - [bvec] s0
| bool SIM::lfsr::get_rev_flag |
( |
| ) |
|
get value of rev_flag
- Note
- when rev_flag is true, output is bit reversed, default value is true,
- Returns
- - [bool] rev_flag
| bvec SIM::lfsr::get_state |
( |
void |
| ) |
|
get state binary vector
- Note
- state is reversed when rev_flag is set
- Returns
- - [bvec] state
| int SIM::lfsr::get_symbol_size |
( |
void |
| ) |
|
get symbol size
- Returns
- - [int] W
| void SIM::lfsr::set_output |
( |
const bvec & |
yout | ) |
|
sets initial/idle output vector
- Note
- yout is a bvec of symbol size (W) length
- Parameters
-
| [in] | yout | - [bvec] y0 = yout |
| void SIM::lfsr::set_poly |
( |
const bvec & |
bpoly | ) |
|
set feedback poly [g0,g1,...,gr] =1+g1*D+g2*D^2+...+gr*D^r
and set default value s0=[10000000...] for reset state and executes reset !
- Note
- set_poly() or set_prbs() are minimal set-up for symbol_size == 1
-
- internally LSB is leftmost, output might be reversed if rev_flag is true
- Parameters
-
| [in] | bpoly | - [bvec] feedback poly |
| void SIM::lfsr::set_prbs |
( |
int |
M | ) |
|
set predefined bpoly for PRBS defined by PRBS sequecne 2^M-1
and execute set_poly() for selected bpoly
- Note
- set_poly() or set_prbs() and set_symbol_size() are minimal set-up
-
- bpoly are defined for [3..9,15,23,31] - source wikipedia, xilinx xapp052.pdf
- Parameters
-
| [in] | M | - [int] power of PRBS sequence size = 2^M-1 |
| void SIM::lfsr::set_reset_state |
( |
const bvec & |
binit | ) |
|
sets value of internal forced by reset s0
- Note
- - only sets variable, does not executes RESET
- Parameters
-
| [in] | binit | - [bvec] initial internal state after RESET |
| void SIM::lfsr::set_rev_flag |
( |
bool |
flag | ) |
|
sets value of rev_flag
- Note
- when rev_flag is true, output is bit reversed, default value is true,
- Parameters
-
| [in] | flag | - [bvec] rev_flag = flag |
| void SIM::lfsr::set_symbol_size |
( |
int |
W | ) |
|
set symbol_size
- Note
- set_poly() or set_prbs() and set_symbol_size() are minimal set-up
-
- for one ce tick LFSR is shifted W times to create on symbol
- Parameters
-
| [in] | W | - [int] number of LFSR shifts and bits in output bmat for one ce tick |
The documentation for this class was generated from the following files:
- C:/jobs/vcc/itpp_sci/include/sim/sim_lfsr.hpp
- C:/jobs/vcc/itpp_sci/sim_lib/code/sim_lfsr.cpp